PIC18F6X2X Datasheet, PDF (213/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
FIGURE 18-27:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
SDA
TBRG
TBRG
SCL
Set SEN, enable START
sequence if SDA = 1, SCL = 1
SEN
BCLIF
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
S
‘0’
SSPIF ^{‘0’}
SCL = 0 before SDA = 0,
bus collision occurs. Set BCLIF.
Interrupt cleared
in software
‘0’
‘0’
FIGURE 18-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SDA = 0, SCL = 1
Set S
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
Set SSPIF
SCL
SEN
BCLIF
S
SCL pulled low after BRG
time-out
Set SEN, enable START
sequence if SDA = 1, SCL = 1
‘0’
S
SSPIF
SDA = 0, SCL = 1,
set SSPIF
Interrupts cleared
in software
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 211