PIC18F6X2X Datasheet, PDF (289/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
BNC
Branch if Not Carry
Syntax:
[ label ] BNC n
Operands:
-128 ≤ n ≤ 127
Operation:
if carry bit is ’0’
(PC) + 2 + 2n → PC
Status Affected: None
Encoding:
1110 0011 nnnn nnnn
Description:
If the Carry bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
No
operation
If No Jump:
Read literal
‘n’
No
operation
Process
Data
No
operation
Write to PC
No
operation
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNC Jump
Before Instruction
PC
= address (HERE)
After Instruction
If Carry =
PC =
If Carry =
PC =
0;
address (Jump)
1;
address (HERE+2)
BNN
Branch if Not Negative
Syntax:
[ label ] BNN n
Operands:
-128 ≤ n ≤ 127
Operation:
if negative bit is ’0’
(PC) + 2 + 2n → PC
Status Affected: None
Encoding:
1110 0111 nnnn nnnn
Description:
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
No
operation
If No Jump:
Read literal
‘n’
No
operation
Process
Data
No
operation
Write to PC
No
operation
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Negative =
PC
=
If Negative =
PC
=
BNN Jump
address (HERE)
0;
address (Jump)
1;
address (HERE+2)
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 287