PIC18F6X2X Datasheet, PDF (224/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
19.1.2 AUTO BAUD RATE DETECT
The enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 19-1) begins whenever a START bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal baud rate generator is used as
a counter to time the bit period of the incoming serial
byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a START bit. The auto baud
detect must receive a byte with the value 55h (ASCII
“U”, which is also the LIN bus Sync character), in order
to calculate the proper bit rate. The measurement is
taken over both a low and a high bit time in order to
minimize any effects caused by asymmetry of the
incoming signal. After a START bit, the SPBRGx
begins counting up using the preselected clock source
on the first rising edge of RX. After eight bits on the RX
pin or the fifth rising edge, an accumulated value total-
ling the proper BRG period is left in the
SPBRGHx:SPBRGx register pair. Once the 5th edge is
seen (this should correspond to the STOP bit), the
ABDEN bit is automatically cleared.
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRGx and SPBRGHx will be used
as a 16-bit counter. This allows the user to verify that
no carry occurred for 8-bit modes by checking for 00h
in the SPBRGHx register. Refer to Table 19-4 for
counter clock rates to the BRG.
While the ABD sequence takes place, the USART state
machine is held in IDLE. The RCIF interrupt is set once
the fifth rising edge on RX is detected. The value in the
RCREGx needs to be read to clear the RCIF interrupt.
RCREGx content should be discarded.
Note 1: If the WUE bit is set with the ABDEN bit,
auto baud rate detection will occur on the
byte following the Break character.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator fre-
quency and USART baud rates are not
possible due to bit error rates. Overall
system timing and communication baud
rates must be taken into consideration
when using the auto baud rate detection
feature.
TABLE 19-4: BRG COUNTER CLOCK
RATES
BRG16 BRGH
BRG Counter Clock
0
0
FOSC/512
0
1
1
Note:
1
FOSC/128
0
FOSC/128
1
FOSC/32
During the ABD sequence, SPBRGx and
SPBRGHx are both used as a 16-bit
counter, independent of BRG16 setting.
FIGURE 19-1:
AUTOMATIC BAUD RATE CALCULATION
BRG Value
RX pin
XXXXh
0000h
Edge #1
START Bit 0 Bit 1
Edge #2
Bit 2 ^{Bit 3}
Edge #3
Bit 4 ^{Bit 5}
Edge #4
Bit 6 ^{Bit 7}
001Ch
Edge #5
STOP Bit
BRG Clock
Set by User
ABDEN bit
RCIF bit
(Interrupt)
Read
RCREGx
SPBRGx
SPBRGHx
XXXXh
XXXXh
Note: The ABD sequence requires the USART module to be configured in Asynchronous mode and WUE = 0.
Auto Cleared
1Ch
00h
DS39612A-page 222
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