PIC18F6X2X Datasheet, PDF (379/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

Bus Collision During a STOP Condition
(Case 1) ........................................................... 213
Bus Collision During a STOP Condition
(Case 2) ........................................................... 213
Bus Collision During START Condition
(SDA only) ........................................................ 210
Bus Collision for Transmit and Acknowledge ........... 209
Capture/Compare/PWM (CCP) ................................ 345
CLKO and I/O .......................................................... 340
Clock Synchronization ............................................. 195
Clock/Instruction Cycle .............................................. 46
Example SPI Master Mode (CKE = 0) ..................... 347
Example SPI Master Mode (CKE = 1) ..................... 348
Example SPI Slave Mode (CKE = 0) ....................... 349
Example SPI Slave Mode (CKE = 1) ....................... 350
External Clock (All Modes except PLL) .................... 339
External Memory Bus Timing for SLEEP
(Microprocessor Mode) ...................................... 79
External Memory Bus Timing for TBLRD
(Extended Microcontroller Mode) ....................... 78
External Memory Bus Timing for TBLRD
(Microprocessor Mode) ...................................... 78
Full-Bridge PWM Output .......................................... 167
Half-Bridge Output ................................................... 165
I²C Bus Data ............................................................ 351
I²C Bus START/STOP Bits ...................................... 351
I²C Master Mode (7 or 10-bit Transmission) ............ 206
I²C Master Mode (7-bit Reception) .......................... 207
I²C Master Mode First START Bit Timing ................ 203
I²C Slave Mode (10-bit Reception, SEN = 0) ........... 192
I²C Slave Mode (10-bit Reception, SEN = 1) ........... 197
I²C Slave Mode (10-bit Transmission) ..................... 193
I²C Slave Mode (7-bit Reception, SEN = 0) ............. 190
I²C Slave Mode (7-bit Reception, SEN = 1) ............. 196
I²C Slave Mode (7-bit Transmission) ....................... 191
Low Voltage Detect .................................................. 256
Master SSP I²C Bus Data ........................................ 353
Master SSP I²C Bus START/STOP Bits .................. 353
Parallel Slave Port (PSP) ......................................... 346
Parallel Slave Port (PSP) Read ............................... 132
Parallel Slave Port (PSP) Write ............................... 131
Program Memory Read ............................................ 341
Program Memory Write ............................................ 342
PWM Auto Shutdown (PRSEN = 0,
Auto Restart Disabled) ..................................... 172
PWM Auto Shutdown (PRSEN = 1,
Auto Restart Enabled) ...................................... 172
PWM Direction Change ........................................... 169
PWM Direction Change at Near
100% Duty Cycle ............................................. 169
PWM Output ............................................................ 156
Repeat START Condition ........................................ 204
RESET, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 343
Send Break Character Sequence ............................ 228
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) .............................. 198
Slave Synchronization ............................................. 181
Slow Rise Time (MCLR Tied to VDD
via 1 kΩ Resistor) ............................................... 40
SPI Mode (Slave Mode with CKE = 0) ..................... 182
SPI Mode (Slave Mode with CKE = 1) ..................... 182
PIC18F6X2X/8X2X
SPI Mode Timing (Master Mode) ............................. 180
STOP Condition Receive or Transmit Mode ............ 208
Synchronous Reception (Master Mode, SREN) ...... 231
Synchronous Transmission ..................................... 229
Synchronous Transmission (Through TXEN) .......... 230
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD via 1 kΩ Resistor) .............. 40
Time-out Sequence on Power-up
(MCLR Not Tied to VDD): Case 1 ...................... 39
Time-out Sequence on Power-up
(MCLR Not Tied to VDD): Case 2 ...................... 39
Time-out Sequence on Power-up (MCLR Tied
to VDD via 1 kΩ Resistor) .................................. 39
Timer0 and Timer1 External Clock .......................... 344
Timing for Transition Between Timer1 and
OSC1 (EC with PLL) .......................................... 27
Timing for Transition Between Timer1 and
OSC1 (HS with PLL) .......................................... 27
Transition Between Timer1 and OSC1
(HS, XT, LP) ...................................................... 26
Transition Between Timer1 and OSC1
(RC, EC) ............................................................ 28
Transition from OSC1 to Timer1 Oscillator ................ 26
USART Synchronous Receive (Master/Slave) ........ 355
USART Synchronous Transmission
(Master/Slave) ................................................. 355
Wake-up from SLEEP via Interrupt .......................... 272
Timing Specifications ....................................................... 339
A/D Conversion Requirements ................................ 357
Capture/Compare/PWM Requirements ................... 345
CLKO and I/O Requirements ............................340, 341
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 347
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 348
Example SPI Mode Requirements
(Slave Mode CKE = 0) ..................................... 349
Example SPI Slave Mode Requirements
(CKE = 1) ......................................................... 350
External Clock Requirements .................................. 339
I²C Bus Data Requirements (Slave Mode) .............. 352
I²C Bus START/STOP Bits Requirements .............. 351
Master SSP I²C Bus Data Requirements ................ 354
Master SSP I²C Bus START/STOP Bits
Requirements .................................................. 353
Parallel Slave Port Requirements ............................ 346
PLL Clock ................................................................ 339
Program Memory Write Requirements .................... 342
RESET, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and
Brown-out Reset Requirements ...................... 343
Timer0 and Timer1 External Clock
Requirements .................................................. 344
USART Synchronous Receive Requirements ......... 355
USART Synchronous Transmission
Requirements .................................................. 355
TRISE Register
PSPMODE Bit ...................................................113, 130
TSTFSZ ........................................................................... 317
Two-Word Instructions
Example Cases .......................................................... 48
TXSTAx Register
BRGH Bit ................................................................. 219
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 377