PIC18F6X2X Datasheet, PDF (290/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
BNOV
Branch if Not Overflow
Syntax:
[ label ] BNOV n
Operands:
-128 ≤ n ≤ 127
Operation:
if overflow bit is ’0’
(PC) + 2 + 2n → PC
Status Affected: None
Encoding:
1110 0101 nnnn nnnn
Description:
If the Overflow bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
No
operation
If No Jump:
Read literal
‘n’
No
operation
Process
Data
No
operation
Write to PC
No
operation
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Overflow =
PC
=
If Overflow =
PC
=
BNOV Jump
address (HERE)
0;
address (Jump)
1;
address (HERE+2)
BNZ
Branch if Not Zero
Syntax:
[ label ] BNZ n
Operands:
-128 ≤ n ≤ 127
Operation:
if zero bit is ’0’
(PC) + 2 + 2n → PC
Status Affected: None
Encoding:
1110 0001 nnnn nnnn
Description:
If the Zero bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
No
operation
If No Jump:
Read literal
‘n’
No
operation
Process
Data
No
operation
Write to PC
No
operation
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNZ Jump
Before Instruction
PC
= address (HERE)
After Instruction
If Zero = 0;
PC = address (Jump)
If Zero = 1;
PC = address (HERE+2)
DS39612A-page 288
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 2003 Microchip Technology Inc.