PIC18F6X2X Datasheet, PDF (350/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
FIGURE 27-15: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
bit 6 - - - - - -1
75, 76
SDI
MSb In
bit 6 - - - -1
74
Note: Refer to Figure 27-4 for load conditions.
LSb
LSb In
TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
71
TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
—
73A TB2B
Last clock edge of Byte 1 to the 1st clock edge of 1.5 TCY + 40 —
Byte 2
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
TdoR
SDO data output rise time PIC18F6X2X/8X2X
—
25
PIC18LF6X2X/8X2X
45
76
TdoF
SDO data output fall time
—
25
78
TscR
SCK output rise time
PIC18F6X2X/8X2X
—
25
(Master mode)
PIC18LF6X2X/8X2X
45
79
TscF
SCK output fall time (Master mode)
—
25
80
TscH2doV, SDO data output valid after PIC18F6X2X/8X2X
—
50
TscL2doV SCK edge
PIC18LF6X2X/8X2X
100
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
—
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS39612A-page 348
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 2003 Microchip Technology Inc.