PIC18F6X2X Datasheet, PDF (125/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
FIGURE 10-17: MCLR/VPP/RG5 PIN BLOCK DIAGRAM
MCLRE
Data Bus
RD TRISA
RD LATA
Schmitt
Trigger
Latch
QD
EN
MCLR/VPP/RG5
RD PORTA
High Voltage Detect
Internal MCLR
Filter
HV
Low Level
MCLR Detect
TABLE 10-13: PORTG FUNCTIONS
Name
Bit# Buffer Type
Function
RG0/CCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG4/CCP5/P1D
bit 0
ST
Input/output port pin, Capture3 input/Compare3 output/PWM3 output,
or Enhanced PWM3 output P3A.
bit 1
ST
Input/output port pin, Addressable USART2 Asynchronous Transmit, or
Addressable USART2 Synchronous Clock.
bit 2
ST
Input/output port pin, Addressable USART2 Asynchronous Receive, or
Addressable USART2 Synchronous Data.
bit 3
ST
Input/output port pin, Capture4 input/Compare4 output/PWM4 output,
or Enhanced PWM3 output P3D.
bit 4
ST
Input/output port pin, Capture5 input/Compare5 output/PWM5 output,
or Enhanced PWM1 output P1D.
MCLR/VPP/RG5
bit 5
ST
Legend: ST = Schmitt Trigger input
Master Clear input or programming voltage input (if MCLR is enabled).
Input only port pin or programming voltage input (if MCLR is
disabled).
TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTG
LATG
TRISG
Legend:
Note 1:
—
— RG5⁽¹⁾ Read PORTG pin/Write PORTG Data Latch
—
—
— LATG Data Output Register
—
—
— Data Direction Control Register for PORTG
x = unknown, u = unchanged
RG5 is available as an input only when MCLR is disabled.
Value on
POR, BOR
Value on
all other
RESETS
--0x xxxx --0u uuuu
---x xxxx ---u uuuu
---1 1111 ---1 1111
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 123