PIC18F6X2X Datasheet, PDF (40/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
PORTJ
PORTH
PORTG⁽⁷⁾
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
xxxx xxxx
xxxx xxxx
---x xxxx
uuuu uuuu
xxxx uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
PORTF
PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
uuuu uuuu
PORTE
PORTD
PORTC
PORTB
PORTA^(5,6)
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx 0000⁽⁵⁾
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu 0000⁽⁵⁾
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu⁽⁵⁾
SPBRGH1 PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
uuuu uuuu
BAUDCON1 PIC18F6X2X PIC18F8X2X
-1-0 0-00
-1-0 0-00
-1-u u-uu
SPBRGH2 PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
uuuu uuuu
BAUDCON2
ECCP1DEL
TMR4
PR4
T4CON
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
-1-0 0-00
0000 0000
0000 0000
1111 1111
-000 0000
-1-0 0-00
0000 0000
0000 0000
1111 1111
-000 0000
-1-u u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
CCPR4H
PIC18F6X2X PIC18F8X2X
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCPR4L
PIC18F6X2X PIC18F8X2X
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCP4CON PIC18F6X2X PIC18F8X2X
--00 0000
--00 0000
--uu uuuu
CCPR5H
PIC18F6X2X PIC18F8X2X
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCPR5L
CCP5CON
SPBRG2
RCREG2
TXREG2
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
xxxx xxxx
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TXSTA2
PIC18F6X2X PIC18F8X2X
0000 -010
0000 -010
uuuu -u1u
RCSTA2
PIC18F6X2X PIC18F8X2X
0000 000x
0000 000x
uuuu uuu-
ECCP3AS
PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
uuuu uuuu
ECCP3DEL PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
uuuu uuuu
ECCP2AS
PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
uuuu uuuu
ECCP2DEL PIC18F6X2X PIC18F8X2X
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1:
2:
3:
4:
5:
6:
7:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 3-2 for RESET value for specific condition.
Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
If MCLR function is disabled, PORTG<5> is a read only bit.
DS39612A-page 38
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 2003 Microchip Technology Inc.