PIC18F6X2X Datasheet, PDF (351/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
FIGURE 27-16: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
70
71
72
80
MSb
83
78
79
79
bit 6 - - - - - -1
78
LSb
SDI
Note:
75, 76
MSb In
74
73
bit 6 - - - -1
Refer to Figure 27-4 for load conditions.
77
LSb In
TABLE 27-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ input
TssL2scL
TCY
—
71
TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
—
73A TB2B
Last clock edge of Byte 1 to the first clock edge of Byte 2 1.5 TCY + 40 —
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
TdoR
SDO data output rise time
PIC18F6X2X/8X2X
—
25
PIC18F6X2X/8X2X
45
76
TdoF
SDO data output fall time
—
25
77
TssH2doZ SS ↑ to SDO output hi-impedance
10
50
78
TscR
SCK output rise time (Master mode) PIC18F6X2X/8X2X
—
25
PIC18F6X2X/8X2X
45
79
TscF
SCK output fall time (Master mode)
—
25
80
TscH2doV, SDO data output valid after SCK PIC18F6X2X/8X2X
—
50
TscL2doV edge
PIC18F6X2X/8X2X
100
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 349