PIC18F6X2X Datasheet, PDF (295/386 Pages) Microchip Technology – 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D

PIC18F6X2X/8X2X
CLRF
Clear f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
[ label ] CLRF f [,a]
0 ≤ f ≤ 255
a ∈ [0,1]
000h → f
1→Z
Z
0110 101a ffff ffff
Clears the contents of the specified
register. If ‘a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will
be selected as per the BSR value
(default).
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
CLRF
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
FLAG_REG,1
0x5A
0x00
CLRWDT
Clear Watchdog Timer
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
[ label ] CLRWDT
None
000h → WDT,
000h → WDT postscaler,
1 → TO,
1 → PD
TO, PD
0000 0000 0000 0100
CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. STATUS
bits TO and PD are set.
1
1
Q Cycle Activity:
Q1
Q2
Decode
No
operation
Q3
Process
Data
Q4
No
operation
Example:
CLRWDT
Before Instruction
WDT Counter
=
After Instruction
WDT Counter
=
WDT Postscaler =
TO
=
PD
=
?
0x00
0
1
1
 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 293