GMS30C2116 Datasheet, PDF (95/322 Pages) Hynix Semiconductor – USERS MANUAL

INSTRUCTION SET
3-31
3.25 Branch Instructions
The Branch instruction BR, and any of the conditional Branch instructions when the
branch condition is met, place the branch address PC + rel (relative to the address of the
first byte after the Branch instruction) in the program counter PC and clear the cache-mode
flag M; all condition flags remain unchanged. Then instruction execution proceeds at the
branch address placed in the PC.
When the branch condition is not met, the M flag and the condition flags remain un-
changed and instruction execution proceeds sequentially.
Besides these explicit Branch instructions, the instructions MOV, MOVI, ADD, ADDI,
SUM, SUB may denote the PC as a destination register and thus be executed as an implicit
branch; the M flag is cleared and the condition flags are set or cleared according to the
specified instruction. All other instructions, except Compare instructions, must not be used
with the PC as destination, otherwise possible Range Errors caused by these instructions
would lead to ambiguous results on backtracking.
Format is PCrel
Notation or alternative Operation
Comment
BLE rel
if N = 1 or Z = 1 then BR;
-- Less or Equal signed
BGT rel
if N = 0 and Z = 0 then BR;
-- Greater Than signed
BLT rel BN rel
if N = 1 then BR;
-- Less Than signed
BGE rel BNN rel if N = 0 then BR;
-- Greater or Equal signed
BSE rel
if C = 1 or Z = 1 then BR;
-- Smaller or Equal unsigned
BHT rel
if C = 0 and Z = 0 then BR;
-- Higher Than unsigned
BST rel BC rel
if C = 1 then BR;
-- Smaller Than unsigned
BHE rel BNC rel if C = 0 then BR;
-- Higher or Equal unsigned
BE rel BZ rel
if Z = 1 then BR;
-- Equal
BNE rel BNZ rel if Z = 0 then BR;
-- Not Equal
BV rel
if V = 1 then BR;
-- oVerflow
BNV rel
if V = 0 then BR;
-- Not oVerflow
BR rel
PC := PC + rel; M := 0;
Note: rel is signed to allow forward or backward branches.
Instruction
Loop1:
MOVI L0, $1234
BLE Loop1
BNE Loop1
; if N=1 or Z=1 then branch
; if Z=0 then branch