GMS30C2116 Datasheet, PDF (65/322 Pages) Hynix Semiconductor – USERS MANUAL

INSTRUCTION SET
3-1
3. Instruction Set
3.1 Memory Instructions
The memory instructions load data from memory in a register Rs (or a register pair
Rs//Rsf) or store data from Rs (or Rs//Rsf) to memory using the data types byte
unsigned/signed, half word unsigned/signed, word or double-word. Since I/O devices are
also addressed by memory instructions, "memory" stands here interchangeably also for I/O
unless memory or I/O address space is specifically denoted.
The memory address is either specified by the operand Rd or Ld, by the sum Rd plus a
signed displacement or by the displacement alone, depending on the address mode.
Memory accesses to words and double-words ignore bits one and zero of the address,
memory accesses to half words ignore bit zero of the address, (since these operands are
located at word or half word boundaries respectively, these address bits are redundant).
If the content of any register Rd except SR is zero, the memory is not accessed and a trap
to Pointer Error occurs (see section 4. Exceptions). Thus, uninitialized pointers are
automatically checked.
Load and Store instructions are pipelined to a total depth of two word entries for Load and
Store, thus, a double-word Load or a double-word Store instruction can be executed
without halting the processor in a wait state. (The address pipeline provides a depth of two
addresses common to load and store).
Double-word memory instructions enter two separate word entries into the pipeline and
start two independent memory cycles. The first memory cycle, loading or storing the high-
order word, uses the address specified by the address mode, the second cycle uses this
address incremented by four and also places it on the address bus.
Accessing data in the same DRAM memory page by any number of succeeding memory
cycles is performed in page mode.
Memory instructions leave all condition flags unchanged.