GMS30C2116 Datasheet, PDF (46/322 Pages) Hynix Semiconductor – USERS MANUAL

1-26
CHAPTER 1
1.8 Instruction Cache (continued)
¡ Ü In the cycle preceding the execution cycle of a memory instruction or any potentially
branch-causing instruction (regardless of whether the branch is taken) except a forward
Branch or Delayed Branch instruction with an instruction length of one half word and a
branch target contained in the cache. Halting the prefetch in these cases avoids filling
the load pipeline with demands for lower priority (compared to data) or potentially
unnecessary instruction words.
l During the execution cycle of any instruction accessing memory or I/O.
Instruction decoding is as follows:
The cache is read in the decode cycle by using bits 6..1 of the PC as an address to the first
half word of the instruction presently being decoded. The instruction decode needs and
uses only the number (1, 2 or 3) of instruction half words defined by the instruction format.
Since only the bits 6..1 of the PC are used for addressing, the half word addresses wrap
around modulo 64. Idle wait cycles are inserted when the instruction is not or not fully
available in the cache.
At an explicit Branch or Delayed Brach instruction:
At an explicit Branch or Delayed Branch instruction (except when placed as delay
instruction) with an instruction length of one half word, the location of the branch target is
checked. The branch target is treated as being in the cache when the target address of a
backward branch is not lower than the address in the look-back counter and the target
address of a forward branch is not higher than two words above the address in the look-
ahead counter. That is, the two instruction words succeeding the instruction word
addressed by the content of the look-ahead counter are treated by a forward branch as
being in the cache. Their actual fetch overlaps in most cases with the execution of the
branch instruction and thus, no cycles are wasted. When the branch target is in the cache,
the look-back counter and the look-ahead counter remain unchanged.
When a branch is taken by a Delayed Branch instruction with an instruction length of one
half word to a forward branch target not in the cache and the cache mode flag M is enabled
(1), the look-back counter and the look-ahead counter remain unchanged. Wait cycles are
then inserted until the ongoing prefetch has loaded the branch target instruction into the
cache.
Any other branch taken flushes the cache by also placing the branch address in the look-
back and the look-ahead counter. Prefetch then starts immediately at the branch address.
Instruction decoding waits until the branch target instruction is fully available in the cache.
The cache mode flag M (bit four of the SR) can be set or cleared by logical instructions. It
is automatically cleared by a Frame instruction and by any branch taken except a branch
caused by a Delayed Branch or Return instruction; a Delayed Branch instruction leaves the
M flag unchanged and a Return instruction restores the M flag from the saved status
register SR.
Note: Since up to eight instruction words can be loaded into the cache by the prefetch, only
24 instruction words are left to be contained in a program loop. Thus, a program loop can
have a maximum length of 96 or 94 bytes including the branch instruction closing the loop,
depending on the even or odd half word address location of the first instruction of the loop
respectively.