GMS30C2116 Datasheet, PDF (137/322 Pages) Hynix Semiconductor – USERS MANUAL

BUS INTERFACE
6-15
6.4.4 IRAM Refresh Test
Bit 20 of the MCR specifies the internal RAM (IRAM) refresh test. The default setting is
normal mode, MCR(20) = 0 specifies refresh test mode.
6.4.5 IRAM Refresh Rate
Bits 18..16 of the MCR specify the IRAM refresh rate in number (2..128) of processor
cycles. The default setting is disabled.
6.4.6 Entry Table Map
Bits 14..12 of the MCR map the entry table (see section 2.4. Entry Table) to one of the
memory areas MEM0..MEM3 or to the IRAM. With a mapping to MEM3 (default setting),
the entry table is mapped to the end of MEM3, with all other settings, the entry table is
mapped to the beginning of the specified memory area.
6.4.7 MEMx Bus Hold Break
Bits 11..8 specify a memory bus hold break for MEM3..MEM0 respectively. The default
setting is disabled. With enabled, bus hold cycles are skipped when the next memory access
addresses the same memory area. Regularly, the bus hold break should be enabled; it must
only be left disabled to accommodate (rare) SRAMs or ROMs which need all specified
cycles before a new access can be started (e.g. for charge restore).