GMS30C2116 Datasheet, PDF (127/322 Pages) Hynix Semiconductor – USERS MANUAL

BUS INTERFACE
6.1.2.1 DRAM Access
CLK
Address Bus
high order bits
Address Bus
low order bits
valid
undefined
RAS#
row address
6-5
col. addr. col. addr.
CAS0#..CAS3#
Page Fault
(IO2)
Data Bus
RAS precharge time
1..4 cycles
RAS to CAS delay time CAS access CAS access
1..4 cycles
time
time
1..4 cycles 1..4 cycles
at read access
WE#
Data Bus
(read data)
at write access
WE#
Data Bus
(write data)
Figure 6.5: DRAM Access
Note: The window for PGFLT acceptance is the last cycle of the RAS-to-CAS delay time.