GMS30C2116 Datasheet, PDF (67/322 Pages) Hynix Semiconductor – USERS MANUAL

INSTRUCTION SET
3-3
from the absolute address mode.
In the case of all data types except byte, bit zero of dis is treated as zero for the calculation
of Rd + dis.
Note: Specification of the PC for Rd provides addressing relative to the address of the first
byte after the memory instruction.
Absolute Address Mode:
Notation:
LDxx.A, STxx.A -- xx: any data type
The displacement dis is used as an address into memory address space. Rd must denote the
SR to differentiate this mode from the displacement address mode; the content of the SR is
not used.
LDxx.A 0, Rs, dis
Memory
dis DATA
Rs
DATA
STxx.A 0, Rs, dis
Memory
dis DATA
Rs
DATA
In the case of all data types except byte, address bit zero is supplied as zero.
Note: The displacement provides absolute addressing at the beginning and the end (MEM3
area) of the memory.
I/O Displacement Address Mode:
Notation:
LDxx.IOD, STxx.IOD -- xx: word or double-word data type
The sum of the contents of the destination register Rd plus a signed displacement dis is
used as an address into I/O address space.
LDxx.IOD Rd, Rs, dis
IO
Rd
ADDR
ADDR
ADDR + dis DATA
Rs
DATA
STxx.IOD Rd, Rs, dis
IO
Rd
ADDR
ADDR
ADDR + dis DATA
Rs
DATA
Rd may denote any register except the SR; Rd not denoting the SR differentiates this mode
from the I/O absolute address mode.
Bits one and zero of dis are treated as zero for the calculation of Rd + dis.
Execution of a memory instruction with I/O displacement address mode does not disrupt
any page mode sequence.