GMS30C2116 Datasheet, PDF (33/322 Pages) Hynix Semiconductor – USERS MANUAL

ARCHITECTURE
1-13
At an exception, the following additional action is performed:
¡ Ü Any corresponding accrued-exception flag whose corresponding trap-enable flag is zero
(not enabled) is set to one; all other accrued-exception flags remain unchanged.
¡ Ü If a corresponding trap-enable flag is one (enabled), any corresponding actual-exception
flag is set to one; all other actual-exception flags are cleared. The destination remains
unchanged.
In the present software version, the software emulation routine must branch to the
corresponding user-supplied exception trap handler. The (modified) result, the source
operand, the stack address of the destination operand and the address of the floating-
point instruction are passed to the trap handler. In the future hardware version, a trap to
Range Error will occur; the Range Error handler will then initiate re-execution of the
floating-point instruction by branching to the entry of the corresponding software
emulation routine, which will then act as described before.
The only exceptions that can coincide are Inexact with Overflow and Inexact with
Underflow. An Overflow or Underflow trap, if enabled, takes precedence over an Inexact
trap; the Inexact accrued-exception flag G2(0) must then be set as well.
1.2.4 Stack Pointer SP, G18
G18 is the stack pointer SP. The SP contains the top address + 4 of the memory part of the
stack, that is the address of the first free memory location in which the first local register
would be saved by a push operation (see section 3.29. Frame Instruction for details). Stack
growth is from low to high address.
Bits one and zero of the SP must always be cleared to zero. The SP can be addressed only
via the high global flag H being set. Copying an operand to the SP is a privileged operation.
Note: Stack Pointer SP contains the top address + 4 of the memory part of the stack
(memory part stack), and Frame Pointer FP points to the beginning of the current stack
frame in the local register set (register part stack).
1.2.5 Upper Stack Bound UB, G19
G19 is the upper stack bound UB. The UB contains the address beyond the highest legal
memory stack location. It is used by the Frame instruction to inhibit stack overflow.
Bits one and zero of the UB must always be cleared to zero. The UB can be addressed only
via the high global flag H being set. Copying an operand to the UB is a privileged
operation.
1.2.6 Bus Control Register BCR, G20
G20 is the write-only bus control register BCR. Its content defines the options possible for
bus cycle, parity and refresh control. The BCR defines the parameters (bus timing, refresh
control, page fault and parity error disable) for accessing external memory located in
address spaces MEM0..MEM3. The BCR can be addressed only via the high global flag H
being set. Copying an operand to the BCR is a privileged operation. The BCR register is
described in detail in the bus interface description in section 6.