GMS30C2116 Datasheet, PDF (132/322 Pages) Hynix Semiconductor – USERS MANUAL

6-10
CHAPTER 6
6.3 Bus Control Register BCR
Global register G20 is the write-only bus control register BCR. The BCR defines the
parameters (bus timing, refresh control, page fault and parity error disable) for accessing
external memory located in address spaces MEM0..MEM3.
All bits of the BCR are set to one on Reset. They are intended to be initialized according to
the hardware environment.
The parity checks can be enabled or disabled separately for each of the four address spaces
MEM0..MEM3.
Bits
31
30
29
28
27..24
23
Name
Mem3ParityDisable
Mem2ParityDisable
Mem1ParityDisable
Mem0ParityDisable
Mem3Access
Mem3Hold(2)
Description
Parity check disable for address space MEM3
1 = disabled
0 = enabled
Parity check disable for address space MEM2
1 = disabled
0 = enabled
Parity check disable for address space MEM1
1 = disabled
0 = enabled
Parity check disable for address space MEM0
1 = disabled
0 = enabled
Access time for address space MEM3
1111 = 16 clock cycles
1110 = 15 clock cycles
1101 = 14 clock cycles
1100 = 13 clock cycles
1011 = 12 clock cycles
1010 = 11 clock cycles
1001 = 10 clock cycles
1000 = 9 clock cycles
0111 = 8 clock cycles
0110 = 7 clock cycles
0101 = 6 clock cycles
0100 = 5 clock cycles
0011 = 4 clock cycles
0010 = 3 clock cycles
0001 = 2 clock cycles
0000 = 1 clock cycle
Bus hold time code for address space MEM3 (see table 6.3)