GMS30C2116 Datasheet, PDF (135/322 Pages) Hynix Semiconductor – USERS MANUAL

BUS INTERFACE
6-13
6.4 Memory Control Register MCR
Global register G27 is the write-only memory control register MCR. The MCR controls
additional parameters for the external memory, the internal memory refresh rate, the
mapping of the entry table and the processor power management. All bits of the MCR are
set to one on Reset. They must be initialized according to the hardware environment and
the desired function. The reserved bits must not be changed when the MCR is updated.
Bits Name
Description
31..26
reserved
25
OutputVoltage
1 = Rail-to-Rail
0 = Reduced
24
InputThreshold
1 = Input threshold according to VDD=5.0V
0 = Input threshold according to VDD=3.3V
23
reserved
22
PowerDown
1 = Processor is active
0 = Processor is in power-down mode
21
MEM0MemoryType 1 = Non-DRAM
0 = DRAM
20
IRAMRefreshTest 1 = Normal Mode
0 = Test Mode
19
reserved
18..16 IRAMRefreshRate
111 = Disabled
110 = Refresh every 2 clock cycles
101 = Refresh every 4 clock cycles
100 = Refresh every 8 clock cycles
011 = Refresh every 16 clock cycles
010 = Refresh every 32 clock cycles
001 = Refresh every 64 clock cycles (recommended refresh rate)
000 = Refresh every 128 clock cycles
15
reserved
14..12 EntryTableMap
111 = MEM3
110 = reserved
101 = reserved
100 = reserved
011 = Internal RAM (IRAM)
010 = MEM2
001 = MEM1
000 = MEM0
11
MEM3BusHoldBrea 1 = Break Disabled
k
0 = Break Enabled
10
MEM2BusHoldBrea 1 = Break Disabled
k
0 = Break Enabled
9
MEM1BusHoldBrea 1 = Break Disabled
k
0 = Break Enabled
8
MEM0BusHoldBrea 1 = Break Disabled
k
0 = Break Enabled