GMS30C2116 Datasheet, PDF (105/322 Pages) Hynix Semiconductor – USERS MANUAL

INSTRUCTION SET
3-41
3.31 Fetch Instruction
The instruction execution is halted until a number of at least n/2 + 1 (n = 0, 2, 4..30)
instruction halfwords succeeding the Fetch instruction are prefetched in the instruction
cache. Since instruction words are fetched, one more halfword may be fetched. The
number n/2 is derived by using bits 4..1 of n, bit 0 of n must be zero.
The Fetch instruction must not be placed as a delay instruction; when the preceding branch
is taken, the prefetch is undefined.
The Fetch instruction shares the basic OP-code SETxx, it is differentiated by denoting the
SR for the Rd-code (see section 2.3. Instruction Formats).
n Format
Notation
Operation
0 Rn
.
.
.
.
.
.
30 Rn
FETCH 1
.
.
.
FETCH 16
Wait until 1 instruction halfword is fetched;
Wait until 16 instruction halfwords are fetched
Note: The Fetch instruction supplements the standard prefetch of instruction words. It may
be used to speed up the execution of a sequence of memory instructions by avoiding
alternating between instruction and data memory pages. By executing a Fetch instruction
preceding a sequence of memory instructions addressing the same data memory page, the
memory accesses can be constrained to the data memory page by prefetching all required
instructions in advance.
A Fetch instruction may also be used preceding a branch into a program loop; thus,
flushing the cache by the first branch repeating the loop can be avoided.