GMS30C2116 Datasheet, PDF (151/322 Pages) Hynix Semiconductor – USERS MANUAL

BUS INTERFACE
6-29
6.11 AC Characteristics
The formulas for the AC-characteristics are based on a load capacity of 30 pF on the
concerned signals. To get the real timing values, the actual capacitive load must be taken
into account. This is done by the addition or subtraction of load dependent delay times,
labeled as ∆t_N or ∆t_P respectively (see table 6.10. Load Dependent Delay Times).
Note that only the difference between 30 pF and the actual capacity load must be used for
the calculation of the ∆t values. All signals except CLKIN are referenced to 1.4V. The AC-
characteristics are based on T_CASE = 0 to 85°C, V_CC = 5V ± 0.25V (unless otherwise noted).
∆t_N
60 ps/pF
∆t_P
40 ps/pF
Table 6.10: Load Dependent Delay Times
Note: All signals (except the clock signal itself) are referenced to the corresponding
driving signal, not to the clock input as is usual. This method eliminates the varying delay
times between output signals relative to the clock input signal and allows more precise bus
timing definitions, resulting in faster bus cycles.
6.11.1 Processor Clock
CLKIN
t_CLKWH
t_CLKWL
t_CLK
Figure 6.10: Processor Clock
V_CC
Symbol
Description
5V ± 0.25V
t_CLK
CLK period
t_CLKWH
CLK high time
t_CLKWL
CLK low time
3.3V ± 0.30V t_CLK
CLK period
t_CLKWH
CLK high time
t_CLKWL
CLK low time
Min Time (ns) Max Time (ns)
15
1000
6
-
6
-
25
1000
10
-
10
-
Table 6.11: Processor Clock Times
Note: CLKIN timing is referenced to V_CC/2.