GMS30C2116 Datasheet, PDF (133/322 Pages) Hynix Semiconductor – USERS MANUAL

BUS INTERFACE
6-11
6.3 Bus Control Register BCR (continued)
Bits Name
22..20 Mem2Access
19..18 Mem1Access
17..16 Mem0Access
15
Mem1Hold
14
Mem2Setup
13..12 RefreshSelect
11..10 RasPrecharge
9..8 RasToCas
7
Description
Access time for address space MEM2
111 = 8 clock cycles
110 = 7 clock cycles
101 = 6 clock cycles
100 = 5 clock cycles
011 = 4 clock cycles
010 = 3 clock cycles
001 = 2 clock cycles
000 = 1 clock cycle
Access time for address space MEM1
11 = 4 clock cycles
10 = 3 clock cycles
01 = 2 clock cycles
00 = 1 clock cycle
Access time for address space MEM0
11 = 4 clock cycles (CASx# low in cycles 3 and 4)
10 = 3 clock cycles (CASx# low in cycles 2 and 3)
01 = 2 clock cycles (CASx# low in cycle 2)
00 = 1 clock cycle (CASx# low in second half of cycle)
Bus hold time for address space MEM1
1 = 1 clock cycle
0 = 0 clock cycles
Address setup time for address space MEM2
1 = 1 clock cycle
0 = 0 clock cycles
Refresh rate select (CAS before RAS refresh)
00 = Refresh every 512 clock cycles
01 = Refresh every 256 clock cycles
10 = Refresh every 128 clock cycles
11 = Refresh disabled
RAS precharge time for address space MEM0
(when MEM0 is a DRAM type)
11 = 4 clock cycles
10 = 3 clock cycles
01 = 2 clock cycles
00 = 1 clock cycle
Bus hold time for address space MEM0
(when MEM0 is not a DRAM type)
11 = 3 clock cycles
10 = 2 clock cycles
01 = 1 clock cycle
00 = 0 clock cycles
RAS to CAS delay time
11 = 4 clock cycles
10 = 3 clock cycles
01 = 2 clock cycles
00 = 1 clock cycle
reserved, must be 1