GMS30C2116 Datasheet, PDF (48/322 Pages) Hynix Semiconductor – USERS MANUAL

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CHAPTER 1
1.9 On-Chip Memory (IRAM)
4KBytes of memory are provided on-chip. The on-chip-memory (IRAM) is mapped to the
hex address C000 0000 of the memory address space and wraps around modulo 4K up to
DFFF FFFF. The IRAM is implemented as dynamic memory, needing refresh (DRAM).
The refresh rate must be specified in the MCR bits 18..16 (see section 6.4. Memory
Control Register MCR) before any use (default is refresh disabled). The number given in
MCR(18..16) specifies the refresh rate in CPU clock cycles; e.g. 128 specifies a refresh
cycle automatically inserted every 128 clock cycles. Each refresh cycle refreshes 16 bytes,
thus, 256 refresh cycles are required to refresh the whole IRAM. A high refresh rate does
not degrade performance since the refresh cycles are inserted on idle IRAM cycles
whenever possible.
An access to the IRAM bypasses the access pipeline of the external memory. Thus,
pending external memory accesses do not delay accesses to the IRAM. The IRAM can
hold data as well as instructions. Instruction words from the IRAM are automatically
transferred to the instruction cache on demand; these transfers do not interfere with
external memory accesses. Besides bypassing of the external memory pipeline, memory
instructions accessing the IRAM behave exactly alike those accessing external memory.
The minimum delay for a load access is one cycle; that is, the data is not available in the
cycle after the load instruction. One or more wait cycles are automatically inserted if the
target register of the load is addressed before the data is loaded into the target register.
Attention: For selection between an internal and external memory access, bits 31..29 of the
specified address register are used before calculation of the effective address. Therefore,
the content of the specified address register must point into the IRAM address range. The
IRAM address range boundary must not be crossed when a displacement is being added.