GMS30C2116 Datasheet, PDF (123/322 Pages) Hynix Semiconductor – USERS MANUAL

BUS INTERFACE
6-1
6. Bus Interface
6.1 Bus Control General
The processor provides on-chip all functions for controlling memory and peripheral
devices, including RAS-CAS multiplexing, DRAM refresh and parity generation and
checking. The number of bus cycles used for a memory or I/O access is also defined by the
processor, thus, no external bus controllers are required. All memory and peripheral
devices can be connected directly, pin by pin, without any glue logic.
The memory address space is divided into five partitions as follows:
Address (hex)
Address Space
Memory Type
0000 0000..3FFF FFFF Address Space MEM0 ROM, SRAM, DRAM
4000 0000..7FFF FFFF Address Space MEM1 ROM, SRAM
8000 0000..BFFF FFFF Address Space MEM2 ROM, SRAM
C000 0000..DFFF FFFF Address Space IRAM Internal RAM (IRAM)
E000 0000..FFFF FFFF Address Space MEM3 ROM, SRAM
Table 6.1: Memory Address Spaces
The bus timing, refresh control and parity error disable for memory access is defined in the
bus control register BCR. The bus timing for I/O access is defined by address bits in the
I/O address.
On a memory or I/O access, the address bus signals are valid through the whole access. On
a memory access, the chip select signal for the selected memory area MEM0..MEM3 is
switched to low (active low) through the whole access. On a write access to memory or I/O,
the data bus and the parity signals are also activated and the write enable signal WE# is
switched to low through the whole access.
A bus wait cycle is inserted automatically to guarantee a minimum of one idle cycle
between the end of an output enable signal (OE#, IORD#, CASx# at read) and the
beginning of a subsequent write access. After a DRAM read access with an access time > 2
cycles, an additional bus wait cycle is inserted.
6.1.1 SRAM and ROM Bus Access
On a one-cycle SRAM or EPROM read access, the output enable signal OE# is switched to
low during the second half of the access cycle; on a multi-cycle read access, OE# is
switched to low after the first access cycle and remains low through the rest of the
specified access cycles. On a SRAM write access, the write enable signals WE0#..WE3#
corresponding to the bytes to be written are switched to low analogous to the OE# signal
for single and multiple access cycles.
For memory area MEM2, an address setup cycle preceding the access cycles can be
specified. For MEM0..MEM3, bus hold cycles can be specified. Bus hold cycles are
additional cycles succeeding the access cycles where neither OE# nor WE0#..WE3# is low
but all other bus signals are asserted. The bus hold cycles can be specified to be skipped or
enforced. (see section 6.4.7. MEMx Bus Hold Break).