GMS30C2116 Datasheet, PDF (110/322 Pages) Hynix Semiconductor – USERS MANUAL

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CHAPTER 3
3.33.2 Floating-Point Instructions
The Floating-Point instructions comply with the ANSI/IEEE standard 754-1985. In the
present version, they are executed as Software instructions. The following description
provides a general overview of the architectural integration.
The basic instructions use single-precision (single-word) and double-precision (double-
word) operands. Floating-Point instructions must not be placed as delay instructions (see
3.26. Delayed Branch Instructions).
Except at the Floating-Point Compare instructions, all condition flags remain unchanged to
allow future concurrent execution.
The rounding modes FRM are encoded as:
SR(14) SR(13)
0
0
0
1
1
0
1
1
Description
Round to nearest
Round toward zero
Round toward - infinity
Round toward + infinity
The floating-point trap enable flags FTE and the exception flags are assigned as:
floating-point
trap enable FTE
SR(12)
SR(11)
SR(10)
SR(9)
SR(8)
accrued
exceptions
G2(4)
G2(3)
G2(2)
G2(1)
G2(0)
actual
exceptions
G2(12)
G2(11)
G2(10)
G2(9)
G2(8)
exception type
Invalid Operation
Division by Zero
Overflow
Underflow
Inexact
The reserved bits G2(31..13) and G2(7..5) must be zero.
A floating-point Not a Number (NaN) is encoded by bits 30..19 = all ones in the operand
word containing the exponent; all other bits of the operand are ignored for differentiating a
NaN from a non-NaN.
In the case of an operand word containing a NaN, bit zero = 0 differentiates a quiet NaN,
bit zero = 1 differentiates a signaling NaN; the bits 18..1 may be used to encode further
information.