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| GMS30C2116 Datasheet, PDF (157/322 Pages) Hynix Semiconductor – USERS MANUAL | |||
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BUS INTERFACE
6-35
6.11.5 SRAM Access
CS0#..CS3#
A25..A0
t1
t5
WE0#..WE3#
D31..D0
DP0..DP3
t4
t3
t6
write data
t2
OE#
D31..D0
DP0..DP3
Figure 6.14: SRAM Access
t4
t7
t8
read data
Note: If Mem 0 is not a DRAM type memory, the signal pin RAS# is used as chip select
CS0#.
6.11.5.1 Multi-Cycle Access
Symbol Description
Formula
t1a A25..A13, CS0#..CS3# setup
(number of setup cycles + 1) x tCLK
time to WE0#..WE3#, 0E# (min.) - 3.2 ns + âtP (a) - âtN (b)
t1b Address A12.. A0 setup time to (number of setup cycles + 1) x tCLK
WE0#..WE3#, OE# (min.)
-2.3 ns + âtP (a) - âtP (b)
Note:
(a) refers to capacitive load on signals WE0#.. WE3#,
OE#
(b) refers to capacitive load on signals A25..A0,
CS0#..CS3#
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