GMS30C2116 Datasheet, PDF (73/322 Pages) Hynix Semiconductor – USERS MANUAL

INSTRUCTION SET
3-9
3.1.3 Store Instructions
The Store instructions transfer data from the register Rs or the register pair Rs//Rsf to the
addressed memory location.
In the case of data types word or double-word, one or two words are placed unchanged
from Rs or Rs//Rsf respectively onto the data bus to be stored in the memory.
In the case of byte and half word data types, the low-order byte or half word is placed onto
the data bus at the byte or half word position addressed by bits one and zero or bit one of
the memory address respectively; it is implied to be merged (via byte write enable) with
the other data in the same memory word.
In the case of signed byte and signed half word data types, any content of Rs exceeding the
value range of the specified data type causes a trap to Range Error. The byte or half word
is stored regardless of a Range Error.
If Rs denotes the SR, zero is stored regardless of the content of SR (or of SR//G2 at
double-word).
Execution of a Store instruction enters the contents of Rs, memory address bits one and
zero and a code for the data type into the store pipeline, places the memory address onto
the address bus and starts a memory cycle. A double-word Store instruction enters the
contents of Rsf and the same control information into the store pipeline as a second entry,
places the memory address incremented by four onto the address bus and starts a second
memory cycle.
After execution of a Store instruction, the next instructions are executed without waiting
for the store memory cycle to finish. The data at the head of the store pipeline is put on the
data bus on demand from the on-chip memory control logic and its pipeline entry is deleted.
When Rsf denotes the same register as Rd (or Ld) at double-word instructions with next
address or post-increment address mode, the incremented content of Rsf is stored in the
second memory cycle; in all other cases, the unchanged content of Rs or Rsf is stored.
Format
LR
LR
RRdis
RRdis
RRdis
Notation
STxx.R Ld, Rs
STxx.P Ld, Rs
STxx.D Rd, Rs, dis
STxx.A 0, Rs, dis
STxx.IOD Rd, Rs, dis
Operation
Data Type xx
Ld^ := Rs;
[(Ld + 4)^ := Rsf;]
-- register address mode
W,D
Ld^ := Rs; Ld := Ld + size;
-- size = 4 or 8
[(old Ld + 4)^ := Rsf;]
-- post-increment address mode
W,D
(Rd + dis)^ := Rs;
[(Rd + dis + 4)^ := Rsf;]
-- displacement address mode
BU,BS,HU,HS,W,D
dis^ := Rs;
[(dis + 4)^ := Rsf;]
-- absolute address mode
BU,BS,HU,HS,W,D
(Rd + dis)^ := Rs;
[(Rd + dis + 4)^ := Rsf;]
-- I/O displacement address mode
W,D