GMS30C2116 Datasheet, PDF (50/322 Pages) Hynix Semiconductor – USERS MANUAL

2-2
CHAPTER 2
2.2 Instruction Execution
On instruction execution, all bits of the operands participate in the operations, except on
the Shift and Rotate instructions (whereat only the 5 least significant bits of the source
operand are used) and except on the byte and half word Store instructions.
Instruction pipeline is as follows:
Instructions are executed by a two-stage pipeline. In the first stage, the instruction is
fetched from the instruction cache and decoded. In the second stage, the instruction is
executed while the next instruction in the first stage is already decoded.
Register instructions are as follows:
On register instructions executing in one or two cycles, the corresponding source and
destination operand words are read from their registers and evaluated in each cycle in
which they are used. Then the result word is placed in the corresponding destination
register in the same cycle. Thus, on all single-word register instructions executing in one
cycle, the source operand register and the destination operand register may coincide
without changing the effect of the instruction. On all other instructions, the effect of a
register coincidence depends on execution order and must be examined specifically for
each such instruction.
The content of a source register remains unchanged unless it is used coincidentally as a
destination register (except on memory Load instructions).
Conditional flags are changed:
Some instructions set or clear condition flags according to the result and special conditions
occurring during their execution. The conditions may be expressed by single bits, relations
or logical combinations of these. If a condition evaluates to one (true), the corresponding
condition flag is set to one, if it evaluates to zero (false), the corresponding condition flag
is cleared to zero. A trap to Range Error may occur if the specific flags and the destination
are updated.
All instructions may use the result and any flags updated by the preceding instruction. A
time penalty occurs only if the result of a memory Load instruction is not yet available
when needed as destination or source operand. In this case one or more (depending on the
memory access time) idle wait cycles are enforced by a hardware interlock.
Using local registers are as follows:
An instruction must not use any local register of the register sequence beginning with L0
beyond the number of usable registers specified by the current value of the frame length
FL (FL = 0 is interpreted as FL = 16). That is, the value of the corresponding register code
(0..15) addressing a local register must be lower than the interpreted value of the FL
(except with a Call or Frame instruction or some restricted cases). Otherwise, an exception
could overwrite the contents of such a register or the beginning of the register part of the
stack at the SP could be overwritten without any warning when a result is placed in such a
register.
Double-word instructions denote the high-order word (at the lower address). The low-order
word adjacently following it (at the higher address) is implied.
"Old" denotes the state before the execution of an instruction.