GMS30C2116 Datasheet, PDF (122/322 Pages) Hynix Semiconductor – USERS MANUAL

5-2
CHAPTER 5
5.1.2 Timer Register TR
The TR is a 32-bit register that is incremented by one on each time unit modulo 2³². Its
content can be used as the lower word of a double-word integer, representing the time
inclusive date.
The TPR and the TR should be set only once on system initialization, whereby the
following instruction sequence must be observed strictly (interrupts must be locked out):
:
:
FETCH 4
ORI SR, $20
MOV TPR, Lx
ORI SR, $20
MOV TR, Ly
:
:
; set H-flag
; load prescaler register from local register x
; set H-flag
; load timer register from local register y
Note: The Fetch instruction is necessary to prevent insertion of idle cycles during the
prescripted instruction sequence.
5.1.3 Timer Compare Register TCR
The content of the TCR is compared continuously with the content of the timer register TR.
An unsigned modulo comparison is performed according to:
result(31..0) := TR(31..0) - TCR(31..0)
On result(31) = 0, the TR is higher than or equal to the TCR.
When the timer interrupt is enabled (FCR(23) = 0) and the value in the TR is higher than
or equal to the value in the TCR, a timer interrupt is generated. This interrupt is cleared by
loading the TCR with a value higher than the current content of the TR.
Timer interrupts can be masked out by FCR(23) = 1; FCR(23) is set to one on Reset. The
timer interrupt disable bit FCR(23) does not affect the timer and compare function.
A delay time in the TCR is calculated according to the formula:
TCR := current content of TR + number of delay time units
The maximum number of delay time units allowed for this calculation is 2³¹-1.
For example:
TR(31..0)
= hex FFFF FF00
delay time units (= 1000) = hex 0000 03E8
TCR(31..0)
= hex 0000 02E8
Since the modulo comparison is an unsigned operation, only unsigned arithmetic must be
used for calculations with timer and timer compare values. Do not use the N or C flag to
test for the result of the comparison TR - TCR, use only result bit 31!