GMS30C2116 Datasheet, PDF (146/322 Pages) Hynix Semiconductor – USERS MANUAL

6-24
CHAPTER 6
6.9.3 Bus Signal Description (continued)
States Names
Use
O/I DP0..DP3
Data Parity signals. DP0..DP3 represent the bi-directional parity
signals; active high indicates a "one". With the GMS30C2132,
DP0, DP1, DP2 and DP3 correspond to D31..D24, D23..D16,
D15..D8 and D7..D0 respectively. With the GMS30C2116, DP0
and DP1 correspond to D15..D8 and D7..D0 respectively.
At a write access, all data parity signals are activated during the
address setup, write and bus hold cycles.
At a read access, the corresponding data parity signals are
evaluated at the last read access cycle when parity checking for
the addressed memory area is enabled.
Parity "odd" is used, that is, the correct parity bit is "one" when
all bits of the corresponding byte are "zero".
O/Z RAS#
Row Address Strobe. Active low indicates row address strobe
asserted.
RAS# is activated high and then again low when the processor
accesses a new page in the DRAM address space, that is when
any of the (high order) RAS address bits is different from the
RAS address bits of the last DRAM access. RAS# is left low
after any own DRAM access.
RAS# is activated high, low and then high by a refresh cycle.
When the bus is granted to another bus master, the processor
starts the next DRAM access as a RAS access.
At any non-RAS address cycle, RAS# is left unchanged, thus, a
previously selected DRAM page is not affected.
When a SRAM is placed in memory area MEM0, RAS# is used
as the chip select signal for this SRAM.
O/Z CAS0#..CAS3# Column Address Strobe. Active low indicates column address
strobe asserted. CAS0#..CAS3# are only used by a DRAM for
column access cycles and for "CAS before RAS" refresh.
With the GMS30C2132, CAS0#..CAS3# correspond to the
column address enable signals for D31..D24, D23..D16,
D15..D8 and D7..D0 respectively.
With the GMS30C2116, CAS0# and CAS1# correspond to the
column address enable signals for D15..D8 and D7..D0
respectively.
O/Z WE#
Write Enable. WE# is signaled in the same cycle(s) as address
signals. Active low indicates a write access, active high
indicates a read access.
WE# is intended to be used as DRAM Write Enable and as
R/W# for I/O access when IORD# is specified as data strobe
(see IORD#).
Note: WE# can also be used to control bus transceivers when
peripheral devices or slow memories must be separated from the
processor data bus in order to decrease the capacitive load of the
processor data bus.