GMS30C2116 Datasheet, PDF (156/322 Pages) Hynix Semiconductor – USERS MANUAL

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6.11.4 DRAM CAS-Before-RAS Refresh
RAS#
t₁
t₂
CAS0#..CAS3#
Figure 6.13: DRAM CAS-Before-RAS Refresh
CHAPTER 6
Symbol Description
Formula
t₁ CAS0#..CAS3# setup time (min.) at precharge time = 1 cycle:
t_CLKWH + 1.4 ns + ∆t_N (a) - ∆t_N (b)
at precharge time > 1 cycle:
t_CLK + t_CLKWH + 1.4 ns + ∆t_N (a) - ∆t_N (b)
Note:
(a) refers to capacitive load on signal RAS#
(b) refers to capacitive load on signals CAS0#..CAS3#
t₂ CAS0#..CAS3# hold time (min.) (number of RAS to CAS delay cycles +
access cycles -1) x t_CLK
+ t_CLKWL - 2.5 ns + ∆t_N (a) - ∆t_N (b)
Note:
(a) refers to capacitive load on signals CAS0#..CAS3#
(b) refers to capacitive load on signal RAS#