GMS30C2116 Datasheet, PDF (119/322 Pages) Hynix Semiconductor – USERS MANUAL

EXCEPTIONS
4-3
4.2.3 Extended Overflow (continued)
The Extended Overflow exception trap occurs asynchronously to the causing instruction;
thus, the causing instruction cannot be identified by backtracking. Usually, there is only
one instruction in a loop that can cause an Extended Overflow exception; thus, a handler
can identify that instruction. When a second Extended Overflow condition is raised before
the first one caused a trap, it is ored and only one trap is taken.
4.2.4 Parity Error
A Parity Error exception can be enabled individually for each of the memory areas
MEM0..MEM3. When enabled, a parity error on an access to the corresponding memory
area causes a Parity Error exception.
When the Parity Error exception is blocked by a higher-priority exception or by the L flag
being set, the Parity Error condition is saved internally, the exception trap occurs then
when the blocking is released.
The Parity Error condition is cleared only by the exception trap; it is not cleared by setting
any of the disable bits 31..28 in the BCR after a Parity Error condition is saved internally.
The Parity Error exception trap occurs asynchronously to the causing memory instruction.
Since memory accesses are pipelined, a Parity Error exception cannot be related to a
specific memory instruction.
4.2.5 Interrupt
An Interrupt exception is caused by an external interrupt signal, by the timer interrupt or by
an IO3 Control Mode. Since the interrupt-lock flag L is set by the exception processing, no
further interrupts can occur until the L flag is cleared. The interrupt exception processing
sets also the interrupt-mode flag I to one. See also sections 2.4. Entry Tables, 5. Timer and
6.9. Bus Signals.
The I flag is used by the operating system, it must not be cleared by the interrupt handler.
A Return instruction restores the old value from the saved SR automatically.
4.2.6 Trace Exception
A Trace exception occurs after each execution of an instruction except a Delayed Branch
instruction when the trace mode is enabled (trace flag T = 1) and the trace pending flag P is
one. After a Call instruction, a Trace exception is suppressed until the next instruction is
executed regardless of the trace mode being enabled; the T flag is not affected.
The P flag in the saved return status register SR must be cleared by the trace handler to
prevent tracing the same instruction again.
The instruction preceding the Trace exception cannot be backtracked since only potentially
error-causing instructions can and need be backtracked.