GMS30C2116 Datasheet, PDF (93/322 Pages) Hynix Semiconductor – USERS MANUAL

INSTRUCTION SET
3-29
3.22 Test Leading Zeros Instruction
The number of leading zeros in the source operand is tested and placed in the destination
register. A source operand equal to zero yields 32 as a result. All condition flags remain
unchanged.
Format Notation
Operation
LL
TESTLZ Ld, Ls
Ld := number of leading zeros in Ls;
3.23 Set Stack Address Instruction
The frame pointer FP is placed, expanded to the stack address, in the destination register.
The FP itself and all condition flags remain unchanged. The expanded FP address is the
address at which the content of L0 would be stored if pushed onto the memory part of the
stack.
The Set Stack Address instruction shares the basic OP-code SETxx, it is differentiated by
n = 0 and not denoting the SR or the PC.
n
Format Notation
Operation
0
Rn
SETADR Rd Rd := SP(31..9)//SR(31..25)//00 + carry into bit 9
-- SR(31..25) is FP
-- carry into bit 9 := (SP(8) = 1 and SR(31) = 0)
Note: The Set Stack Address instruction calculates the stack address of the beginning of
the current stack frame. L0..L15 of this frame can then be addressed relative to this stack
address in the stack address mode with displacement values of 0..60 respectively.
Provided the stack address of a stack frame has been saved, for example in a global register,
any data in this stack frame can then be addressed also from within all younger generations
of stack frames by using the saved stack address. (Addressing of local variables in older
generations of stack frames is required by all block oriented programming languages like
Pascal, Modula-2 and Ada.)
The basic OP-code SETxx is shared as indicated:
¡ Ü n = 0 while not denoting the SR or the PC differentiates the Set Stack Address
instruction.
¡ Ü n = 1..31 while not denoting the SR or the PC differentiates the Set Conditional
instructions.
¡ Ü Denoting the SR differentiates the Fetch instruction.
¡ Ü Denoting the PC is reserved for future use.
3.24 Set Conditional Instructions
The destination register is set or cleared according to the states of the condition flags
specified by n. The condition flags themselves remain unchanged.
The Set Conditional instructions share the basic OP-code SETxx, they are differentiated by
n = 1..31 and not denoting the SR or the PC.