GMS30C2116 Datasheet, PDF (111/322 Pages) Hynix Semiconductor – USERS MANUAL

INSTRUCTION SET
3-47
3.33.2 Floating-Point Instructions (continued)
The floating-point instruction supports the five IEEE standard 754-1985 exceptions:
l Inexact (I)
l Overflow (O)
l Underflow (U)
l Division by Zero (Z)
l Invalid Operation (V)
The following sections describe the conditions that cause the floating-point instruction to
generate each of its exceptions and the details the floating-point instruction response to
each exception-causing situation.
Inexact Exception (I)
The floating-point instruction generates the Inexact exception if the result of an operation
is not exact or if it overflows.
Floating-point Trap Enabled Results: If Inexact exception traps are enabled, the result
register is not modified and the source registers are preserve.
Floating-point Trap Disabled Results: The rounded or overflowed result is delivered to the
destination register if no other software trap occurs.
Overflow Exception (O)
The Overflow exception is signaled when the magnitude of the rounded floating-point
result, if the exponent range were to be unbounded, is larger than the destination format’s
largest finite number. (This exception also sets the Inexact exception and Flag bits.)
Floating-point Trap Enabled Results: The result register is not modified, and the source
registers are preserved.
Floating-point Trap Disabled Reuslts: The result, when no trap occurs, is determined by
the rounding mode and the sign of the intermediate result.
Division by Zero (Z)
The Division by Zero exception is signaled on and implemented divide operation if the
divisor is zero and the dividend is a finite non-zero number. Software can simulate this
exception for other operations that produce a signed infinity, such as ln(0), sec(π/2), csc(0),
or 0^-1.
Floating-point Trap Enabled Results: The result register is not modified, and the source
register are preserved.
Floating-point Trap Disabled Resutls: The result, when no trap occurs, is a correctly signed
infinity.