GMS30C2116 Datasheet, PDF (23/322 Pages) Hynix Semiconductor – USERS MANUAL

ARCHITECTURE
1-3
each clock cycle and the effective execution rate is one cycle per instruction.
Clock Cycles
Instruction _{#1 F A M W}
#2 _{F A M W}
#3 F A M W
#4 F A M W
Figure 1.2: Multiple Instructions in a Hypothetical Pipeline
(2) Load/Store Architecture
The discussion of the instruction pipeline illustrates how each instruction can be
subdivided into several discrete parts that permit the processor to execute multiple
instructions in parallel. For this technique to work efficiently, the time required to execute
each instruction subpart should be approximately equal. If one part requires an excessive
length of time, there is an unpleasant choice: either halting the pipeline (inserting wait or
idle cycles), or making all cycles longer to accommodate this lengthier portion of the
instruction.
Instructions that perform operations on operands in memory tend to increase either the
cycle time or the number of cycles/instruction. Such instruction require additional time for
execution to calculate the addresses of the operands, read the required operands from
memory, calculate the result, and store the results of the operation back to memory. To
eliminate the negative impact of such instruction, RISC designs implement a load and store
(load/store) architecture in which the processor has many register, all operations are
performed on operands held in processor registers, and main memory is accessed only by
load and store instructions.
This approach produces several benefits
l Reducing the number of memory accesses eases memory bandwidth requirements
l Limiting all operations to registers helps simplicity the instruction set
l Eliminating memory operations makes it easier for compilers to optimize register
allocation - this further reduces memory accesses and also reduces the
instructions/task factor
All of these factors help RISC design approach their goal of executing one
cycle/instruction. However, two classes of instructions hinder achievement of this goal -
load instructions and branch instructions. The following sections discuss how RISC
designs overcome obstacles raised by these classes of instructions.