GMS30C2116 Datasheet, PDF (11/322 Pages) Hynix Semiconductor – USERS MANUAL

Overview
0-1
0. Overview
0.1 GMS30C2116/32 RISC/DSP
The GMS30C2116 and GMS30C2132 RISC/DSP present a new class of microprocessors:
The combination of a high-performance RISC microprocessor with an additional powerful
DSP instruction set and on-chip micro-controller functions. The high throughput is not
achieved by raw clock speed, it is due to a sophisticated novel architecture, combining the
advantages of RISC and DSP technology.
The speed is obtained by an optimized combination of the following features:
¡ Ü The most recent stack frames are kept in a register stack, thereby reducing data memory
accesses to a minimum by keeping almost all local data in registers.
¡ Ü Pipelined memory access allows overlapping of memory accesses with execution.
¡ Ü 4KByte on-chip memory.
¡ Ü On-chip instruction cache omits instruction fetch in inner loops and provides pre-fetch.
¡ ÜVariable-length instructions of 16, 32 or 48 bits provide a large, powerful instruction set,
thereby reducing the number of instructions to be executed.
¡ Ü Primarily used 16-bit instructions halve the memory bandwidth required for instruction
fetch in comparison to conventional RISC architectures with fixed-length 32-bit
instructions, yielding also even better code economy than conventional CISC
architectures.
¡ Ü Regular instruction set allows hardwiring of control logic at low component count.
¡ Ü Most instructions execute in one cycle.
¡ Ü Pipelined DSP instructions.
¡ Ü Parallel execution of ALU and DSP instructions.
¡ Ü Single-cycle half word multiply-accumulate operation.
¡ Ü Fast Call and Return by parameter passing via registers.
¡ Ü An instruction pipeline depth of only two stages - decode/execute - provides branching
without insertion of wait cycles in combination with Delayed Branch instructions.
¡ Ü Range and pointer checks are performed without speed penalty, thus, these checks need
no longer be turned off, thereby providing higher runtime reliability.
¡ Ü Separate address and data buses provide a throughput of one 32-bit word each cycle.
The features noted above contribute to reduce the number of idle wait cycles to a bare
minimum. The processor is designed to sustain its execution rate with a standard DRAM
memory.
The low power consumption is of advantage for mobile (portable) applications or in
temperature-sensitive environments.
In the current version, the GMS30C2116 and GMS30C2132 RISC/DSP are implemented in a
0.6 µm-CMOS-process.
The GMS30C2116 and GMS30C2132 RISC/DSP are based on hyperstone architecture.