GMS30C2116 Datasheet, PDF (26/322 Pages) Hynix Semiconductor – USERS MANUAL

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CHAPTER 1
1.1.3 The pipeline structure of GMS30C2132
GMS30C2132 has a two-stage pipeline structure and each stage is composed of two phases
(TM and TV). The basic structure of GMS30C2132 pipeline is two-stage pipeline, but
actually it is lengthened by the need of some instruction. As an example, standard ALU
instruction uses 5 phases (2 stage pipeline (4 phases) + additional 1 phase). This additional
phase doesn’t use the datapath that is used next instruction, so next instruction executi on
need not wait until previous ALU instruction is ended. DSP instruction takes over 2 stage
pipeline for execution, and requires same resource in the datapath that is required to next
DSP instruction. So next DSP instruction is delayed.
The pipeline structure of GMS30C2132 and the action of datapath are described in Table
1.1.
Stage
Phase
Datapath Action
Fetch/Decode TM (Low) 1. The instruction is read from the instruction cache
according to the address of instruction.
TV (High) 2. The control signal of Rd (destination operand) and Rs
(source operand) is activated according to the instruction
that was loaded in TM phase
2.1 The control signal of IR (immediate register
(operand)) and IL (instruction length) is activated.
2.2 The address of next instruction is calculated and saved
in PC
Execute/Write TM (Low) 1. The next instruction is read from the instruction cache.
1.1 The address of Rs and Rs are determined.
1.2 The immediate operand is determined.
1.3 The operand is read from register stack using the
address of Rs and Rd.
1.4 The operand XR, YR and QR are controlled.
TV (High) 2. The input data of ALU is attained.
2.1 The control of ALU datapath is made and instruction
is executed in ALU.
2.2 The result of ALU operation is saved in the register
file.
Additional
Insertion
Next TM Additional ALU operation is continued and its result is
saved in the register file.
Table 1.1: The pipeline structure of GMS30C2132 and the action of datapath.