GMS30C2116 Datasheet, PDF (13/322 Pages) Hynix Semiconductor – USERS MANUAL

Overview
0-3
0.1. GMS30C2116/32 RISC/DSP (continued)
On-chip Memory:
¡ Ü 4KByte internal (on-chip) memory
Memory Data Types:
¡ Ü Unsigned and signed byte (8 bit)
¡ Ü Unsigned and signed half word (16 bit), located on half word boundary
¡ ÜUndedicated word (32 bit), located on word boundary
¡ Ü Undedicated double-word (64 bit), located on word boundary
Runtime Stack:
¡ Ü Runtime stack is divided into memory part and register part
¡ Ü Register part is implemented by the 64 local registers holding the most recent stack
frame(s)
¡ Ü Current stack frame (maximum 16 registers) is always kept in register part of the stack
¡ Ü Data transfer between memory and register part of the stack is automatic
¡ Ü Upper stack bound is guarded
Instruction Cache:
¡ Ü An on-chip instruction cache reduces instruction memory access substantially
Instructions General:
¡ Ü Variable-length instructions of one, two or three half words halve required memory
bandwidth
¡ Ü Pipeline depth of only two stages, assures immediate refill after branches
¡ Ü Register instructions of type "source operator destination ⇒ destination" or
"source operator immediate ⇒ destination"
¡ Ü All register bits participate in an operation
¡ Ü Immediate operands of 5, 16 and 32 bits, zero- or sign-expanded
¡ Ü Large address displacement of up to 28 bits
¡ ÜTwo sets of signed arithmetical instructions: instructions set or clear either only the
overflow flag or trap additionally to a Range Error routine on overflow
¡ Ü DSP instructions operate on 16-bit integer, real and complex fixed-point data and 32-bit
integer data into 32-bit and 64-bit hardware accumulators
Instruction Summary:
¡ Ü Memory instructions pipelined to a depth of two stages, trap on address register equal to
zero (check for invalid pointers)