GMS30C2116 Datasheet, PDF (134/322 Pages) Hynix Semiconductor – USERS MANUAL

6-12
CHAPTER 6
6.3 Bus Control Register BCR (continued)
Bits Name
6..4 PageSizeCode
3..2 Mem3Hold(1..0)
1..0 Mem2Hold
Description
Page size code (see table 6.4)
Bus hold time code for address space MEM3 (see table 6.3)
Bus hold time for address space MEM2
11 = 3 clock cycles
10 = 2 clock cycles
01 = 1 clock cycle
00 = 0 clock cycles
Table 6.2: Bus Control Register BCR
The bus hold time for address space MEM3 is specified by bits 23 and 3..2 in the BCR as
follows:
BCR(23)
1
1
1
1
0
0
0
0
BCR(3..2) Bus Hold Time
11
7 clock cycles
10
6 clock cycles
01
5 clock cycles
00
4 clock cycles
11
3 clock cycles
10
2 clock cycles
01
1 clock cycle
00
0 clock cycles
Table 6.3: Bus Hold Time for MEM3
The DRAM type used and the physical page size of the DRAM are specified by bits 6..4 in
the BCR. Table 6.4 shows the encoding of BCR(6..4) and the associated column address
ranges for memory areas with bus sizes of 32, 16 and 8 bits.
BCR(6..4)
000
001
010
011
100
101
110
111
Column Address Range
32-bit Bus Size 16-bit Bus Size 8-bit Bus Size
A15..A2
A15..A1
A15..A0
A14..A2
A14..A1
A14..A0
A13..A2
A13..A1
A13..A0
A12..A2
A12..A1
A12..A0
A11..A2
A11..A1
A11..A0
A10..A2
A10..A1
A10..A0
A9..A2
A9..A1
A9..A0
A8..A2
A8..A1
A8..A0