GMS30C2116 Datasheet, PDF(155/322 Page) Hynix Semiconductor – USERS MANUAL

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GMS30C2116 Datasheet, PDF (155/322 Pages) Hynix Semiconductor – USERS MANUAL

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BUS INTERFACE

6-33

6.11.3.2 Single-Cycle Access (continued)

Symbol Description

Formula

t2a Column address A12..A0 hold tCLKWL + 0.1 ns + âtP (a) - âtN (b)

time after CAS0#..CAS3# low

(min.)

Note:

(a) refers to capacitive load on signals A12..A0

(b) refers to capacitive load on signals CAS0#..CAS3#

t2b WE# hold time after

CAS0#..CAS3# low (min.)

tCLKWL + 0.5 ns + âtN (a) - âtN (b)

Note:

(a) refers to capacitive load on signal WE#

(b) refers to capacitive load on signals CAS0#..CAS3#

t3 Column address A12..A0 valid tCLK - 0.1 ns + âtN (a) - âtP (b)

before end of CAS0#..CAS3#

(min.)

Note:

(a) refers to capacitive load on signals CAS0#..CAS3#

(b) refers to capacitive load on signals A12..A0

t4 CAS0#..CAS3# pulse width high tCLKWH - 0.9 ns

(CAS precharge) (min.)

t5 CAS0#..CAS3# pulse width low tCLKWL - 0.9 ns

(min.)

t6 Write data D31..D0, DP0..DP3 tCLKWH - 2.1 ns + âtN (a) - âtN (b)

setup time to CAS0#..CAS3#

(min.)

Note:

(a) refers to capacitive load on signals CAS0#..CAS3#

(b) refers to capacitive load on signals D31..D0,

DP0..DP3

t7 Write data D31..D0, DP0..DP3 tCLKWL + 0.5 ns + âtN (a) - âtN (b)

hold time after CAS0#..CAS3#

low (min.)

Note:

(a) refers to capacitive load on signals D31..D0,

DP0..DP3

(b) refers to capacitive load on signals CAS0#..CAS3#

t8 Read data D31..D0, DP0..DP3 0 ns

setup time to end of

CAS0#..CAS3# (min.)

t9 Read data D31..D0, DP0..DP3 0 ns

hold time (min.)

Note:

Read data is sampled by the skew-compensated

CAS0#..CAS3# signals and latched internally

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