GMS30C2116 Datasheet, PDF (154/322 Pages) Hynix Semiconductor – USERS MANUAL

6-32
6.11.3.1 Multi-Cycle Access (continued)
CHAPTER 6
Symbol Description
Formula
t₃ Column address A12..A0 valid (number of access cycles) x t_CLK
before end of CAS0#..CAS3#
(min)
- 0.1 ns + ∆t_N (a) - ∆t_P (b)
Note:
(a) refers to capacitive load on signals CAS0#..CAS3#
(b) refers to capacitive load on signals A12..A0
t₄ CAS0#..CAS3# pulse width high (number of CAS inactive cycles) x t_CLK - 0.1 ns
(CAS precharge) (min.)
t₅ CAS0#..CAS3# pulse width low (number of CAS active cycles) x t_CLK - 1.4 ns
(min.)
t₆ Write data D31..D0, DP0..DP3 (number of CAS inactive cycles) x t_CLK
setup time to CAS0#..CAS3#
(min.)
- 1.2 ns + ∆t_N (a) - ∆t_N (b)
Note:
(a) refers to capacitive load on signals CAS0#..CAS3#
(b) refers to capacitive load on signals D31..D0,
DP0..DP3
t₇ Write data D31..D0, DP0..DP3 (number of CAS active cycles) x t_CLK
hold time after CAS0#..CAS3#
low (min.)
- 0.1 ns + ∆t_N (a) - ∆t_N (b)
Note:
(a) refers to capacitive load on signals D31..D0,
DP0..DP3
(b) refers to capacitive load on signals CAS0#..CAS3#
t₈ Read data D31..D0, DP0..DP3 0 ns
setup time to end of
CAS0#..CAS3# (min.)
t₉ Read data D31..D0, DP0..DP3 0 ns
hold time (min.)
Note:
Read data is sampled by the skew-compensated
CAS0#..CAS3# signals and latched internally
6.11.3.2 Single-Cycle Access
Symbol Description
t_1a Column address A12..A0 setup
time to CAS0#..CAS3# (min.)
t_1b WE# setup time to
CAS0#..CAS3# (min.)
Formula
t_CLKWH - 1.0 ns + ∆t_N (a) - ∆t_P (b)
Note:
(a) refers to capacitive load on signals CAS0#..CAS3#
(b) refers to capacitive load on signals A12..A0
t_CLKWH - 1.9 ns + ∆t_N (a) - ∆t_N (b)
Note:
(a) refers to capacitive load on signals CAS0#..CAS3#
(b) refers to capacitive load on signal WE#