GMS30C2116 Datasheet, PDF (129/322 Pages) Hynix Semiconductor – USERS MANUAL

BUS INTERFACE
6-7
6.1.3 I/O Bus Access
The bus timing for an I/O access is specified by bits 10..3 of the I/O address.
I/O Address
.......
10 9 8 7 6 5 4 3 2 1 0
Peri. Device Control Mode
0 = IORD# / IOWR#
1 = R/W# / DATA strobe control
Address Set-Up Time
00 = 0 cycle, 01 = 2 cycles
10 = 4 cycles, 11 = 8 cycles
Access Time
000(2), 001(4), 010(6)
011(8), 100(10), 101(12)
110(14), 111(16 cycles)
Reserved
Bus Hold Time after Read/Write Access
i) Access Time < 8 cycles
00(x), 01(1), 10(2), 11(3 cycles)
ii) Access Time > 8 cycles
00(x), 01(1), 10(6), 11(7 cycles)
On an I/O access, the I/O read strobe IORD# or the I/O write strobe IOWR# is switched
low for a read or write access respectively after the first access cycle and remains low for
the rest of the specified access cycles. The beginning of the IORD# or IOWR# signal can
be delayed by more than one cycle by specifying additional address setup cycles preceding
the access cycles. The beginning of the next bus access can be delayed by specifying bus
hold cycles succeeding the access cycles. Bus hold cycles are required by many I/O
devices due to the time required to switch from driving the data bus to three-state.
When an I/O device requires R/W# direction and data strobe control, IORD# can be
specified (by address bit 10 = 1) as data strobe. WE# is then used as R/W# signal.
6.1.3.1 I/O Read Access
CLK
Chip Select
Address Bus
WE#
IORD#
Data Bus
Address
setup time
0..6 cycles
Figure 6.7: I/O Read Access
Access time
2..16 cycles
Bus hold
time
1..7 cycles