GMS30C2116 Datasheet, PDF (153/322 Pages) Hynix Semiconductor – USERS MANUAL

BUS INTERFACE
6-31
6.11.3 DRAM Fast Page Mode Access
A12..A0
WE#
CAS0#..
CAS3#
column address
t₁
t₂
t₃
t₄
t₅
t₆
t₇
D31..D0
DP0..DP3
write data
t₈ t₉
D31..D0
DP0..DP3
read data
Figure 6.12: DRAM Fast Page Mode Access
6.11.3.1 Multi-Cycle Access
Symbol Description
t_1a Column address A12..A0
setup time to CAS0#..CAS3#
t_1b WE# setup time
to CAS0#..CAS3#
t_2a Column address A12..A0
hold time after CAS0#..CAS3#
low (min.)
t_2b WE# hold time after
CAS0#..CAS3# low (min.)
Formula
(number of CAS inactive cycles) x t_CLK
- 0.1 ns + ∆t_N (a) - ∆t_P (b)
Note:
(a) refers to capacitive load on signals CAS0#..CAS3#
(b) refers to capacitive load on signals A12..A0
(number of CAS inactive cycles) x t_CLK
- 1.1 ns + ∆t_N (a) - ∆t_N (b)
Note:
(a) refers to capacitive load on signals CAS0#..CAS3#
(b) refers to capacitive load on signal WE#
(number of CAS active cycles) x t_CLK
- 0.5 ns + ∆t_P (a) - ∆t_N (b)
Note:
(a) refers to capacitive load on signals A12..A0
(b) refers to capacitive load on signals CAS0#..CAS3#
(number of CAS active cycles) x t_CLK
- 0.1 ns + ∆t_N (a) - ∆t_N (b)
Note:
(a) refers to capacitive load on signal WE#
(b) refers to capacitive load on signals CAS0#..CAS3#