GMS30C2116 Datasheet, PDF (60/322 Pages) Hynix Semiconductor – USERS MANUAL

2-12
CHAPTER 2
2.5 Instruction Timing
The following execution times are given in number of processor clock cycles.
All instructions not shown below: 1 cycle
Move Double-Word: 2 cycles
Shift Double-Word: 2 cycles
Test Leading Zeros: 2 cycles
Multiply word:
when both operands are in the range of -2¹⁵..2¹⁵-1: 4 cycles
all other cases: 5 cycles
Multiply double-word signed:
when both operands are in the range of -2¹⁵..2¹⁵-1: 5 cycles
all other cases: 6 cycles
Multiply double-word unsigned:
when both operands are in the range of 0..2¹⁶-1: 4 cycles
all other cases: 6 cycles
Divide unsigned and signed: 36 cycles
Branch instructions when branch not taken: 1 cycle
when branch taken and target in on-chip cache: 2 cycles
when branch taken and target in memory : 2 + memory read latency cycles
(see next page)
Delayed Branch instructions when branch not taken: 1 cycle
when branch taken and target in on-chip cache: 1 cycle
when branch taken and target in memory: 1 + memory read latency cycles exceeding
(delay instruction cycles - 1)
Call and Trap instructions when branch not taken: 1 cycle
when branch taken: 2 + memory read latency cycles
Software instructions: 6 + memory read latency cycles exceeding 4 cycles
Frame when not pushing words on the stack: 3 cycles
additionally when pushing n words on the stack: memory write latency cycles
+ n * bus cycles per access
-- write latency = cycles elapsed until write access cycle of first word stored
(minimum = 1 at a non-RAS access and no pipeline congestion)
Return:
4 + memory read latency cycles exceeding 2 cycles
additionally when pulling n words from the stack: memory RAS latency
+ n * bus cycles per access
(RAS latency applies only at n > 2, otherwise RAS latency is always 0)
-- RAS latency = RAS precharge cycles + RAS to CAS delay cycles