GMS30C2116 Datasheet, PDF (45/322 Pages) Hynix Semiconductor – USERS MANUAL

ARCHITECTURE
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1.8 Instruction Cache
The instruction cache is transparent to programs. A program executes correctly even if it
ignores the cache, whereby it is assumed that the instruction code is not modified in the
local range contained in the cache.
The instruction cache holds a total of up to 128 bytes (32 unstructured 32-bit words of
instructions). It is implemented as a circular buffer that is guarded by a look-ahead counter
and a look-back counter. The look-ahead counter holds the highest and the look-back
counter the lowest address of the instruction words available in the cache. The cache-mode
flag M is used to optimize special cases in loops (see details below). The cache can be
regarded as a temporary local window into the instruction sequence, moving along with
instruction execution and being halted by the execution of a program loop.
l Look-Ahead Counter: It holds the highest address of instruction word in the
instruction cache (the start address of the instruction cache). Bits 6..2 of the look-
ahead counter represent the location of the prefetched instruction to be saved in the
instruction cache.
l Look-Back Counter: It holds the lowest address of instruction word in the
instruction cache (the end address of the instruction cache).
l Cache Mode Flag M: It represents whether the instruction cache is available (M=1)
or flushed (M=0). It is automatically cleared by a Frame instruction and by any
branch taken except a delayed branch.
Its function is as follows:
The prefetch control loads unstructured 32-bit instruction words (without regard to instruc-
tion boundaries) from memory into the cache. The load operation is pipelined to a depth of
two stages (see section 1.1.1 The pipeline structure of GMS30C2132 for details of the
instruction pipeline). The look-ahead counter is incremented by four at each prefetch cycle.
It always contains the address of the last instruction word for which an address bus cycle is
initiated, regardless of whether the addressed instruction word is in the load pipeline or
already loaded into the instruction cache.
The prefetched instruction word is placed in the cache word location addressed by bits 6..2
of the look-ahead counter. The look-back counter remains unchanged during prefetch
unless the cache word location, it addresses with its bits 6..2, is overwritten by a prefetched
instruction word. In this case, it is incremented by four to point to the then lowest-
addressed usable instruction word in the cache. Since the cache is implemented as a
circular buffer, the cache word addresses derived from bits 6..2 of the look-ahead and look-
back counter wrap around modulo 32.
The prefetch is halted:
¡ Ü When eight words are prefetched, that is, eight words are available (including those
pending in the load pipeline) in the prefetch sequence succeeding the instruction word
addressed by the program counter PC through the instruction word addressed by the
look-ahead counter. Prefetch is resumed when the PC is advanced by instruction
execution.