GMS30C2116 Datasheet, PDF (228/322 Pages) Hynix Semiconductor – USERS MANUAL

A-54
Delayed Branch on Greater Than
Appendix A. Instruction Set Details
DBGT
Format:
PCrel format
15
87 6
0
OP-code
0
low-rel
S
1110 1011
S: sign bit of rel
rel = 25 S // low-rel // 0
range -128 ~ 126
Notation:
DBGT rel
Description:
If the negative flag N and the zero flag Z are cleared (N = 0 and Z = 0), place the branch
address PC + rel (relative of the first byte after the Branch instruction) in the program
counter PC. All condition flags and the cache mode flag M remain unchanged.
Then the instruction after the Delayed Branch instruction, called the delay instruction, is
executed regardless of whether the delayed branch is taken or not taken.
When the delayed branch is not taken, the delay instruction is executed like a regular
instruction. The PC and the ILC are updated accordingly and instruction execution
proceeds sequentially.
When the delayed branch is taken, the delay instruction is executed before execution
proceeds at the branch target. The PC (containing the delayed-branch target address) is not
updated by the delay instruction. Any reference to the PC by the delay instruction
references the delayed-branch target address.
Operation:
If N = 0 & Z = 0 then
PC := PC + rel
Exceptions:
None.