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| GMS30C2116 Datasheet, PDF (160/322 Pages) Hynix Semiconductor – USERS MANUAL | |||
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6-38
6.11.5.2 Single-Cycle Access (continued)
CHAPTER 6
Symbol Description
t7 Read data D31..D0, DP0..DP3
setup time to end of OE# (min.)
t8 Read data D31..D0, DP0..DP3
hold time (min.)
Formula
0 ns
0 ns
Note:
Read data is sampled by the skew-compensated
OE# signal and latched internally
6.11.6 I/0 Access
A25..A13
WE#
t1
IOWR#,
IORD#
D31..D0
D31..D0
Figure 6.15: I/O Access
t2
t3
t4
t5
write data
t6
t7
read data
Symbol Description
t1 A25..A13, WE# setup time
before IOWR#, IORD# (min.)
t2 A25..A13, WE# hold time after
IOWR#, IORD# (min.)
t3 IOWR#, IORD# pulse width low
(min.)
Formula
(number of setup cycles + 1) x tCLK
- 1.1 ns + âtN (a) - âtN (b)
Note:
(a) refers to capacitive load on signals IOWR#,
IORD#
(b) refers to capacitive load on signals A25..A13
(number of bus hold cycles) x tCLK
- 0.5 ns + âtN (a) - âtN (b)
Note:
(a) refers to capacitive load on signals A25..A13
(b) refers to capacitive load on signals IOWR#,
IORD#
(number of access cycles - 1) x tCLK
- 2.0 ns
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