GMS30C2116 Datasheet, PDF (34/322 Pages) Hynix Semiconductor – USERS MANUAL

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CHAPTER 1
1.2.7 Timer Prescaler Register TPR, G21
G21 is the write-only timer prescaler register TPR. It adapts the timer clock to different
processor clock frequencies. The TCR can be addressed only via the high global flag H
being set. Copying an operand to the TPR is a privileged operation. The TPR is described
in the timer description in section 5.
1.2.8 Timer Compare Register TCR, G22
G22 is the timer compare register TCR. Its content is compared continuously with the
content of the timer register TR. The TCR can be addressed only via the high global flag H
being set. Copying an operand to the TCR is a privileged operation. The TCR is described
in the timer description in section 5.
1.2.9 Timer Register TR, G23
G23 is the timer register TR. Its content is incremented by one on each time unit. The TR
can be addressed only via the high global flag H being set. Copying an operand to the TR
is a privileged operation. The TR is described in the timer description in section 5.
1.2.10 Watchdog Compare Register WCR, G24
G24 is the watchdog compare register WCR. The WCR can be addressed only via the high
global flag H being set. The WCR is used by the IO3 control mode (Watchdog Mode
FCR(13) = 1, FCR(12) = 0). Copying an operand to the WCR is a privileged operation.
The WCR is described in the bus interface description in section 6.
1.2.11 Input Status Register ISR, G25
G25 is the read-only input status register ISR. The ISR reflects the input levels at the pins
IO1..IO3 as well as the input levels at the four interrupt pins INT1..INT4 and contains the
EvenFlag and the EqualFlag. The ISR can be addressed only via the high global flag H
being set. The ISR is described in the bus interface description in section 6.
1.2.12 Function Control Register FCR, G26
G26 is the write-only function control register FCR. The FCR controls the polarity and
function of the I/O pins IO1..IO3 and the interrupt pins INT1..INT4, the timer interrupt
mask and priority, the bus lock and the Extended Overflow exception. The FCR can be
addressed only via the high global flag H being set. Copying an operand to the FCR is a
privileged operation. The FCR is described in the bus interface description in section 6.