GMS30C2116 Datasheet, PDF (47/322 Pages) Hynix Semiconductor – USERS MANUAL

ARCHITECTURE
1-27
1.8 Instruction Cache (continued)
A forward Branch or Delayed Branch instruction with an instruction length of one half
word into up to two instruction words succeeding the word addressed by the look-ahead
counter treats the branch target as being in the cache and does not flush the cache. Thus,
three or four instruction half words, depending on the odd or even half word address
location of the branch instruction respectively, can always be skipped without flushing the
cache.
Enabling the cache-mode flag M is only required when a program loop to be contained in
the cache contains a forward branch to a branch target in the program loop and more than
three (or four, see above) instruction half words are to be skipped. In this case, the enabled
M flag in combination with a Delayed Branch instruction with an instruction length of one
half word inhibits flushing the cache when the branch target is not yet prefetched.
Fetch instruction is as follows:
Since a single-word memory instruction halts the prefetch for two cycles, any sequence of
memory instructions, even with interspersed one-cycle non-memory instructions, halts the
prefetch during its execution. Thus, alternating between instruction and data memory pages
is avoided. If the number of instruction half words required by such a sequence is not
guaranteed to be in the cache at the beginning of the sequence, a Fetch instruction
enforcing the prefetch of the sequence may be used. A Fetch instruction may also be used
preceding a branch into a program loop; thus, flushing the cache by the first branch
repeating the loop can be avoided.
At a Branch of Delayed Branch instruction with an instruction length of two half words:
A branch taken caused by a Branch or Delayed Branch instruction with an instruction
length of two half words always flushes the instruction cache, even if the branch target is
in the cache. Thus, branches can be forced to bypass the cache, thereby reducing the cache
to a prefetch buffer. This reduced function can be used for testing.
The last nine words of a memory block (except at the highest ROM memory block)
must not contain any instruction to be executed, otherwise the prefetch could overrun
the memory limit.