GMS30C2116 Datasheet, PDF (57/322 Pages) Hynix Semiconductor – USERS MANUAL

INSTRUCTIONS GENERAL
2-9
2.4 Entry Tables (continued)
Table 2.7 shows the trap entries when the entry table is mapped to the beginning of
memory areas MEM0, MEM1, MEM2 or IRAM. x is 0, 4, 8 or C corresponding to the
mapping to MEM0, MEM1, MEM2 or IRAM respectively.
Address (Hex) Entry Description
x000 0000
TRAP 63 Error entry for instruction code of all ones
x000 0004
TRAP 62 Reserved
-- priority 0 (highest)
x000 0008
TRAP 61 Reserved
-- priority 1
x000 000C
TRAP 60 Range, Pointer, Frame and Privilege Error
-- priority 2
x000 0010
TRAP 59 Extended Overflow
-- priority 3
x000 0014
TRAP 58 Parity Error
-- priority 4
x000 0018
TRAP 57 Trace Exception
-- priority 16
x000 001C
TRAP 56 Reserved
-- priority 17 (lowest)
x000 0020
TRAP 55 Timer Interrupt
-- priority selectable as 6, 8, 10, 12
x000 0024
TRAP 54 IO3 Interrupt
-- priority 5
x000 0028
TRAP 53 INT1 Interrupt
-- priority 7
x000 002C
TRAP 52 INT2 Interrupt
-- priority 9
x000 0030
TRAP 51 INT3 Interrupt
-- priority 11
x000 0034
TRAP 50 INT4 Interrupt
-- priority 13
x000 0038
TRAP 49 IO1 Interrupt
-- priority 14
x000 003C
TRAP 48 IO2 Interrupt
-- priority 15
:
:
x000 00F8
TRAP 1
x000 00FC
TRAP 0
Table 2.7: Trap entry table mapped to the beginning of MEM0, MEM1, MEM2 or IRAM